Pascal and Francis Bibliographic Databases

Help

Search results

Your search

kw.\*:("High level synthesis")

Document Type [dt]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Publication Year[py]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Discipline (document) [di]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Author Country

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Results 1 to 25 of 209

  • Page / 9
Export

Selection :

  • and

Allocation of multiple precision behaviors for maximal bit level reuse of hardware resourcesMOLINA, M. C; MENDIAS, J. M; HERMIDA, R et al.Journal of systems architecture. 2003, Vol 49, Num 12-15, pp 505-519, issn 1383-7621, 15 p.Article

A fragmentation aware High-Level Synthesis flow for low power heterogenous datapathsDEL BARRIO, Alberto A; OGRENCI MEMIK, Seda; MOLINA, María C et al.Integration (Amsterdam). 2013, Vol 46, Num 2, pp 119-130, issn 0167-9260, 12 p.Article

Abstraction in Hardware System DesignNIKHIL, Rishiyur S.Communications of the ACM. 2011, Vol 54, Num 10, pp 36-44, issn 0001-0782, 9 p.Article

A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesisXIANWU XING; CHING CHUEN JONG.Microelectronics journal. 2007, Vol 38, Num 4-5, pp 595-605, issn 0959-8324, 11 p.Article

PuMA++: From behavioral specification to multi-FPGA-prototypeHARBICH, Klaus; BARKE, Erich.Lecture notes in computer science. 2001, pp 133-141, issn 0302-9743, isbn 3-540-42499-7Conference Paper

Memory allocation and mapping in high-level synthesis: An integrated approachSEO, Jaewon; KIM, Taewhan; PREETI RANJAN PANDA et al.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 5, pp 928-938, issn 1063-8210, 11 p.Article

Performance-driven scheduling of behavioural specificationsMOLINA, M. C; RUIZ-SAUTUA, R; GARCIA-REPETTO, P et al.Integration (Amsterdam). 2009, Vol 42, Num 3, pp 294-303, issn 0167-9260, 10 p.Conference Paper

ANALYSE SÉMANTIQUE DE DESCRIPTIONS VHDL SYNCHRONES EN VUE DE LA SYNTHÈSE = SEMANTIC ANALYSIS OF SYNCHRONOUS VHDL DESCRIPTIONS FOR RTL SYNTHESISJacomme, Ludovic; Greiner, Alain.1999, 261 p.Thesis

Enhancing scheduling solutions through ant colony optimizationKOPURI, Shekhar; MANSOURI, Nazanin.IEEE International Symposium on Circuits and Systems. 2004, pp 257-260, isbn 0-7803-8251-X, 4 p.Conference Paper

Scheduling and Resource Binding Algorithm Considering Timing VariationJUNG, Jongyoon; KIM, Taewhan.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 2, pp 205-216, issn 1063-8210, 12 p.Article

Fixed Point Data Type Modeling for High Level Synthesis : Circuits and Design Techniques for Advanced Large Scale IntegrationSCHAFER, Benjamin Carrion; IGUCHI, Yusuke; TAKAHASHI, Wataru et al.IEICE transactions on electronics. 2010, Vol 93, Num 3, pp 361-368, issn 0916-8524, 8 p.Article

High Performance and Area Efficient Flexible DSP Datapath SynthesisXYDIS, Sotirios; ECONOMAKOS, George; SOUDRIS, Dimitrios et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 3, pp 429-442, issn 1063-8210, 14 p.Article

Accurate TSV Number Minimization in High-Level SynthesisLEE, Chih-Hung; HUANG, Shih-Hsu; CHENG, Chun-Hua et al.Journal of information science and engineering. 2011, Vol 27, Num 5, pp 1527-1543, issn 1016-2364, 17 p.Article

Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined DatapathXIANWU XING; CHING CHUEN JONG.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 9, pp 1348-1352, issn 1063-8210, 5 p.Article

Power-Aware High-Level Synthesis With Clock Skew ManagementYEH, Tung-Hua; WANG, Sying-Jyan.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 1, pp 167-171, issn 1063-8210, 5 p.Article

Algorithms for TSV resource sharing and optimization in designing 3D stacked ICsBYUNGHYUN LEE; TAEWHAN KIM.Integration (Amsterdam). 2014, Vol 47, Num 2, pp 184-194, issn 0167-9260, 11 p.Article

A PN-based approach to the high-level synthesis of digital systemsSHEN, Victor R. L.Integration (Amsterdam). 2006, Vol 39, Num 3, pp 182-204, issn 0167-9260, 23 p.Article

Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and LatchesINOUE, Keisuke; KANEKO, Mineo.IEICE transactions on fundamentals of electronics, communications and computer science. 2013, Vol 96, Num 8, pp 1712-1722, issn 0916-8508, 11 p.Article

Input data reuse in compiling window operations onto reconfigurable hardwareZHI GUO; BUYUKKURT, Betul; NAJJAR, Walid et al.ACM SIGPLAN notices. 2004, Vol 39, Num 7, pp 249-256, issn 1523-2867, 8 p.Conference Paper

Memory Allocation for Multi-Resolution Image ProcessingKOBAYASHI, Yasuhiro; HARIYAMA, Masanori; KAMEYAMA, Michitaka et al.IEICE transactions on information and systems. 2008, Vol 91, Num 10, pp 2386-2397, issn 0916-8532, 12 p.Article

Generation of heterogeneous distributed architectures for memory-intensive applications through high-level synthesisCHAO HUANG; RAVI, Srivaths; RAGHUNATHAN, Anand et al.IEEE transactions on very large scale integration (VLSI) systems. 2007, Vol 15, Num 11, pp 1191-1204, issn 1063-8210, 14 p.Article

Complexity reduction of digital filters using shift inclusive differential coefficientsHUNSOO CHOO; MUHAMMAD, Khurram; ROY, Kaushik et al.IEEE transactions on signal processing. 2004, Vol 52, Num 6, pp 1760-1772, issn 1053-587X, 13 p.Article

Introduction de la prédiction de branchement dans la synthèse de haut niveau = Branch prediction for high-level synthesisLAPOTRE, Vianney; COUSSY, Philippe; CHAVET, Cyrille et al.TSI. Technique et science informatiques. 2013, Vol 32, Num 2, pp 281-301, issn 0752-4072, 21 p.Article

Synthèse de haut niveau tenant compte de la dynamique des traitements : Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveauLE GAL, Bertrand; CASSEAU, Emmanuel; ANDRIAMISAINA, Caaliph et al.TSI. Technique et science informatiques. 2008, Vol 27, Num 9-10, pp 1129-1154, issn 0752-4072, 26 p.Article

High-level technology mapping for memoriesHAIFENG ZHOU; ZHENGHUI LIN; WEI CAO et al.Computing and informatics. 2003, Vol 22, Num 5, pp 427-438, issn 1335-9150, 12 p.Article

  • Page / 9